The present invention relates to a semiconductor device having an analog-digital converter.
An A/D converter performs analog-to-digital conversion on an analog signal input from plural channels by switching the channels. In many cases, the A/D converter is supplied with a mix of a signal requiring high-speed processing and a signal requiring low-speed processing. In such a case, a processing delay might occur, that is, the A/D conversion might be uncompleted for a signal requiring high-speed processing by the specified time.
For example, Japanese Unexamined Patent Publication No. 2010-41152 (patent document 1) discloses the technology of decreasing processing delays. According to the technology described in this document, an A/D converter is set to start for a channel and then an asynchronous A/D conversion request might occur for a channel different from the already set channel before the A/D converter starts for that channel. In such a case, the A/D converter is reset to start so that the A/D conversion will start after a lapse of specified time in consideration of the time to perform the A/D conversion on plural channels that requested the A/D conversion.
Patent Document 1: Japanese Unexamined Patent Publication No. 2010-41152